Double-ring network system, method for determining transmission priority in double-ring network and transmission station device

ABSTRACT

According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port A at an A-system side, a communication port B at a B-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization. This reduces a transmission time.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a Divisional of U.S. application Ser. No. 13/336,142, filed Dec.23, 2011, which is based upon and claims the benefit of priority fromJapanese Patent Application No. 2010-293159, filed Dec. 28, 2010, theentire contents of both of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a double-ring networksystem, a method for determining a transmission priority in adouble-ring network, and a transmission station device.

BACKGROUND

There is a token-ring method (hereinafter simply called “token-ring”)for transmitting or receiving data between nodes (transmission stations)connected to a transmission line such as a LAN (local area network).Generally, in token-ring, a token is defined and constantly circles in atransmission line. This prevents frames from colliding each other on thetransmission line. Namely, the token-ring differs from CSMA/CD methodand can avoid the collision.

For example, Patent document 1 (Japanese Published Unexamined PatentApplication No. 2004-166074) discloses a data transmission method inwhich a transmission station eligible to transmit a frame is controlledby a token, one transmission station is set as a synchronous node fromamong transmission stations, and a synchronous frame (SYN frame)including information as to whether or not a transmission station isactive, which is transmitted by the synchronous node, is used.

Patent document 2 (Japanese Published Unexamined Patent Application No.2008-131132) discloses a data transmission method in token-ring in whichthe token-ring has a ring topology where two or more transmissionstations each of which has two communication ports allowing two-waycommunication are connected in a ring shape, any adjacent twotransmission stations are set to be terminal stations, any transmissionstation is set to be a synchronous node, and transmission is controlledwhile a frame transmitted beyond the terminal station is set to beinvalid.

These data transmission methods described in Patent documents 1 and 2avoid frame collision by limiting to one the number of transmissionstations (nodes) eligible to transmit a frame on a transmission lineusing a token for the predetermined duration. For example, atransmission station starts transmission to a master station in order ofincreasing a node number which is set as a token order. Thus, the lengthof time of transmission to the master station largely varies dependingon the assignment of node number in the token-ring network system.

For example, there is a problem that a transmission time necessary for asynchronous time by a synchronous frame largely varies between a casewhere transmission stations are connected in a ring shape whose nodenumbers are assigned in order of transmission priority previously setand a case where transmission stations are connected in a ring shapewhose node numbers are not assigned in order of transmission prioritypreviously set. The latter case brings delayed accumulation betweentransmission stations, which causes delay of transmission time.

In the token-ring network system, there is a possibility that atransmission station is changed or added. In this case, it is necessaryto create a loss-free network system where an operator determines atransmission priority of the transmission station and connects thetransmission station on the transmission line in view of thetransmission priority such that delay of transmission time does notoccur. However, the operator is burdened with the creation of networksystem in view of a transmission priority.

Patent documents 1 and 2 disclose the methods in which the masterstation accepts an REQ frame from only a node which is allowed totransmit it by the master station, during MAC control time. Thus, in acase where 256 transmission stations (including a master station) enterinto the transmission line, the master station needs to perform 256scans using SYN frames. This requires a great deal of time until alltransmission stations are allowed to transmit an REQ frame to the masterstation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structure diagram in a control method of adouble-ring network according to a first exemplary embodiment.

FIG. 2 is an explanatory diagram that illustrates a transmissionpriority according to the first exemplary embodiment.

FIG. 3 is an explanatory diagram that illustrates a relationship betweena live list and an address list according to the first exemplaryembodiment.

FIG. 4 is a schematic structure diagram of a logical address determiningcircuit portion and an address list setting circuit portion according tothe first exemplary embodiment.

FIG. 5 is an explanatory diagram that illustrates determinationprocessing of the logical address determining circuit portion accordingto the first exemplary embodiment.

FIG. 6A is an explanatory diagram that illustrates determinationprocessing of the logical address determining circuit portion accordingto a second exemplary embodiment.

FIG. 6B is an explanatory diagram that illustrates the determinationprocessing of the logical address determining circuit portion accordingto a second exemplary embodiment.

FIG. 7 is a schematic structure diagram of the live list setting circuitportion according to the first exemplary embodiment.

FIG. 8 is a sequence diagram in the control method of the double-ringnetwork according to the first exemplary embodiment.

FIG. 9 is a sequence diagram in the control method of the double-ringnetwork according to the first exemplary embodiment.

FIG. 10 is an explanatory diagram that illustrates synchronous framesaccording to the first and second exemplary embodiments.

FIG. 11 is an explanatory diagram that illustrates frames in a zeroperiod according to the first exemplary embodiment.

FIG. 12 is an explanatory diagram that illustrates frames in a firstperiod according to the first exemplary embodiment.

FIG. 13 is an explanatory diagram that illustrates frames in a secondperiod according to the first exemplary embodiment.

FIG. 14 is an explanatory diagram that illustrates frames in a thirdperiod according to the first exemplary embodiment.

FIG. 15 is an explanatory diagram that illustrates frames in a fourthperiod according to the first exemplary embodiment.

FIG. 16 is an explanatory diagram that illustrates frames in a fifthperiod according to the first exemplary embodiment.

FIG. 17 is an explanatory diagram that illustrates an address listgenerated when a transmission station enters into a loop according tothe first exemplary embodiment.

FIG. 18 is an explanatory diagram that illustrates an address listgenerated when a transmission station enters into the loop according tothe first exemplary embodiment.

FIG. 19 is an explanatory diagram that illustrates an address listgenerated when a transmission station enters into the loop according tothe first exemplary embodiment.

FIG. 20 is a schematic structure diagram in a control method of adouble-ring network according to the second exemplary embodiment.

FIG. 21 is an explanatory diagram that illustrates connection requestframes at a time when a hub enters into a loop according to the firstand second exemplary embodiments.

FIG. 22 is an explanatory diagram that illustrates an address listgenerated when a hub enters into the loop according to the secondexemplary embodiment.

FIG. 23 is an explanatory diagram that illustrates an address listgenerated when a hub enters into the loop according to the secondexemplary embodiment.

FIG. 24 is an explanatory diagram that illustrates an address listgenerated when a hub enters into the loop according to the secondexemplary embodiment.

FIG. 25 is an explanatory diagram that illustrates an address listgenerated when a hub enters into the loop according to the secondexemplary embodiment.

FIG. 26 is an explanatory diagram that illustrates an address listgenerated when a hub withdraws from the loop according to the secondexemplary embodiment.

DETAILED DESCRIPTION

According to one embodiment, a double-ring network system includes oneor more transmission stations each of which is connected to adouble-ring network and includes two communication ports allowingtwo-way communication. Any one of the one or more transmission stationsfunctions as a master station. A new transmission station, which entersinto the double-ring network, transmits a connection request frameincluding a physical address of the new transmission station, accordingto a reception of a synchronous frame from the master station. Themaster station associates the transmitted physical address with alogical address for determining a transmission priority of eachtransmission station connected to the double-ring network, to determinea transmission priority of the new transmission station. The masterstation includes: a transmitting and receiving portion that controls atransmission and reception timing, transmits a generated frame from thetwo communication ports, and introduces therein a frame received via thedouble-ring network according to a transmission of a synchronous frame;a frame detection determining circuit portion that determines whether ornot the transmitting and receiving portion receives the connectionrequest frame; an address list setting circuit portion that includestransmission priority setting circuits to which logical addresses aresequentially assigned, and transmits a physical address of atransmission station set in each transmission priority setting circuitand a logical address of the each transmission priority setting circuitin which the physical address of the transmission station is set; alogical address determining circuit portion that determines, when theframe detection determining circuit portion receives the connectionrequest frame, a logical address whose a value corresponds to aconnection number of the new transmission station such that transmissionpriorities of transmission stations match a connection order on thedouble-ring network, and sets the physical address included in theconnection request frame in a transmission priority setting circuit towhich the determined logical address is assigned; and a frame datagenerating circuit portion that generates a synchronous frame to which aphysical address and a logical address from the address list settingcircuit are added, and instructs the transmitting and receiving portionto transmit the generated synchronous frame.

According to one embodiment, a method for determining a transmissionpriority of a transmission station connected to a double-ring networksystem to which one or more transmission stations each of which isconnected to the double-ring network and includes two communicationports allowing two-way communication are connected, wherein any one ofthe one or more transmission stations functions as a master station. Themethod includes: generating, via the master station, an address list inwhich one or more logical addresses for determining one or moretransmission priorities of the one or more transmission stationsconnected to the double-ring network are arranged in ascending order;transmitting, via the master station, to the one or more transmissionstations connected to the double-ring network a synchronous frame whichincludes therein the one or more logical addresses associated with oneor more physical addresses of the one or more transmission stations;transmitting, via a new transmission station to be connected to thedouble-ring network, to the master station a connection request framewhich includes a physical address of the new transmission station;setting, when each transmission station other than the master stationreceives the synchronous frame, a logical address included in thesynchronous frame as a transmission priority of the each transmissionstation and transmitting, via the each transmission station, a framedata to the master station according to its own transmission priority;associating, via the master station, on the address list the physicaladdress included in the connection request frame transmitted from thenew transmission station according to a transmission of the synchronousframe, with a logical address whose a value corresponds to a connectionnumber of the new transmission station such that transmission prioritiesof transmission stations match a connection order on the double-ringnetwork; obtaining, via the master station, when receiving theconnection request frame in a state where physical addresses areassigned on the address list, logical addresses generated by adding oneto each of logical addresses equal to or more than the logical addressassociated with the physical address included in the connection requestframe, and associating with the obtained logical addresses physicaladdresses associated with the logical addresses equal to or more thanthe logical address; and transmitting, via the master station, everytime when a physical address is assigned on the address list, to thedouble-ring network the synchronous frame to which the physical addressand a logical address associated with the physical address are added.

According to one embodiment, a transmission station device which isconnected to a double-ring network and includes two communication portsallowing two-way communication. The transmission station deviceincludes: a transmitting and receiving portion that controls atransmission and reception timing, transmits a generated frame from thetwo communication ports, and introduces therein a frame received via thedouble-ring network according to a transmission of a synchronous frame;a frame detection determining circuit portion that determines whether ornot the transmitting and receiving portion receives a connection requestframe from a new transmission station; an address list setting circuitportion that includes transmission priority setting circuits to whichlogical addresses indicative of transmission priorities on thedouble-ring network are sequentially assigned, and transmits a physicaladdress of a transmission station set in each transmission prioritysetting circuit and a logical address of the each transmission prioritysetting circuit in which the physical address of the transmissionstation is set; a logical address determining circuit portion thatdetermines, when the frame detection determining circuit portionreceives the connection request frame, a logical address whose a valuecorresponds to a connection number of the new transmission station suchthat transmission priorities of transmission stations match a connectionorder on the double-ring network, and sets the physical address includedin the connection request frame in a transmission priority settingcircuit to which the determined logical address is assigned; and a framedata generating circuit portion that generates a synchronous frame towhich a physical address and a logical address from the address listsetting circuit are added, and instructs the transmitting and receivingportion to transmit the generated synchronous frame.

In first and second exemplary embodiments, transmission priorities ofnodes at a synchronous time are controlled to reduce the synchronoustime. In this data transmission method, frame collision is avoided bylimiting to one the number of nodes eligible to transmit a frame on atransmission line for the predetermined duration. Namely, by introducinga shortest path function in the data transmission method according tothe first and second embodiments, a token order is determined such thatthe token order does not depend on physical addresses of transmissionstations and is matched to a connection order of transmission stationsto realize path optimization.

The first and second embodiments will be described hereinafter withreference to the accompanying drawings. In each drawing, the same orsimilar symbol is assigned to the same or similar element. It is notedthat each drawing shows a typical structure of device, system or thelike which differs from a real structure of device, system or the like.Accordingly, a concrete structure should be determined with reference tothe following description. It goes without saying that one drawing mayinclude a different part in a structure similar to another drawing.

As the first exemplary embodiment, it will be described thattransmission station nodes “i”, which include a master station, enterinto or withdraw from a double-ring network system (simply called“loop”). More specifically, transmission station nodes “i” (1≦i≦5; nodes1 to 5) are connected to (or disconnected from) a loop as the firstexemplary embodiment. As the second exemplary embodiment, it will bedescribed that a transmission station hub “i” enters into a double-ringnetwork system and branching station nodes “i” are connected (star-likeconnected) to the transmission station hub “i”.

First Exemplary Embodiment

FIG. 1 is a schematic structure diagram in a control method of adouble-ring network according to a first exemplary embodiment. Thedouble-ring network includes two or more transmission stations each ofwhich allows two-way communication and enters into the double-ringnetwork. It is desirable to set any adjacent two transmission stationsto be terminal stations and any transmission station to be a masterstation.

Each transmission station has the same structure as the master station.Each transmission station has a means for holding a transmissionpriority (logical address) of its own node informed by the masterstation, and a means for transmitting from its own node a transmissionframe, which includes a connection request frame, a complete frame andthe like, according to the transmission priority.

As shown in FIG. 2 (a), in the data transmission method disclosed inPatent document 1, a token is ordered in order of node address (physicaladdress) at a synchronous time, which uniquely determines a transmissionpriority in order of node address. For example, nodes A and B arerespectively set to be priority nodes 1 and 2.

The master node has a structure shown in FIG. 1 and determines a tokenorder (transmission priority “0”, “1”, “2”, “3”, “4” . . . ; also called“logical address”) in order of node connection by introducing a shortestpath function, to realize path optimization, without depending on nodeaddresses ((1), (2), (3), (4), (5) . . . ; also called “physicaladdress”) (see FIG. 2 (b)). This reduces a transmission time. In thedrawings, values of physical addresses correspond to numerical numbersin parenthesis and values of logical addresses correspond to numericalnumbers in square brackets.

(Structure of Each Element)

As shown in FIG. 1, the master station (node 1) includes a transmittingand receiving permission switch portion 10, and an A-system (clockwise)side communication port 20 (also called communication port A) and aB-system (anticlockwise) side communication port 30 (also calledcommunication port B) that are connected to the transmitting andreceiving permission switch portion 10. The communication port 20 has areceiver (RVR-A) and a transmitter (TVR-A) to perform two-waycommunication with an adjacent transmission station. The communicationport 30 has a receiver (RVR-B) and a transmitter (TVR-B) to performtwo-way communication with an adjacent transmission station.

A first receiving control circuit portion 40 is connected to thetransmitting and receiving permission switch portion 10. A MAC/DLC(hereinafter called transmitting and receiving control circuit portion)50 is connected to the first receiving control circuit portion 40. Thetransmitting and receiving permission switch portion 10, a framedetection determining circuit portion 60 and a frame data generatingcircuit portion 70 are connected to the transmitting and receivingcontrol circuit portion 50. The transmitting and receiving permissionswitch portion 10, the first receiving control circuit portion 40 andthe transmitting and receiving control circuit portion 50 arecollectively called a transmitting and receiving portion.

A logical address determining circuit portion 80 is connected to theframe detection determining circuit portion 60. A live list settingcircuit portion 90 (also simply called live list or LL) and an addresslist setting circuit portion 100 (also simply called address list or AL)are connected to the logical address determining circuit portion 80. Thelogical address determining circuit portion 80 and the address listsetting circuit portion 100 are collectively called a shortest pathfunction.

A computer portion 110 is connected to the live list setting circuitportion 90 and the address list setting circuit portion 100 andinstructs the frame data generating circuit portion 70 to generate acertain frame. A physical address setting portion 120 is connected tothe computer portion 110.

The master station does not determine a transmission priority accordingto physical addresses of transmission stations (nodes), but has theshortest path function that carries out control and setting such thatthe logical address determining circuit portion 80 determines logicaladdresses of transmission stations in order of node connection in thenetwork and respectively associates physical addresses of transmissionstations with the determined logical addresses.

Each element will be described below in detail.

The address list setting circuit portion 100 manages transmissionpriorities of transmission stations, which have physical addresses M(e.g., (1) to (5)), connected to the double-ring network using ahardware. The physical addresses are node addresses that are previouslyand uniquely assigned to the transmission stations and do not overlapone another. The address list setting circuit portion 100 includes apredetermined number (e.g., 256) of transmission priority settingcircuits 101 (e.g., D-FF (D-type flip-flop)) to which numerical numbers(e.g., 0, 1, 2 . . . 255) are sequentially assigned (see FIG. 4). Atransmission priority setting circuit 101 holds a physical address M,which is determined by the logical address determining circuit portion80, based on a logical address in response to an address modification ENsignal.

Namely, the transmission priority setting circuits 101 are arranged inorder of the assigned numerical numbers, determine transmissionpriorities of the transmission stations, which have the physicaladdresses M, in order of the numerical numbers of the transmissionpriority setting circuits 101 without depending on the physicaladdresses M, and set the transmission priorities to the nodes. Thisallows each transmission station to transmit a transmission frameaccording to its own transmission priority when receiving an SYN frame,which reduces a transmission time. The conventional master stationaccepts an REQ frame from only nodes which are allowed to transmit it bythe master station during MAC control time. Thus, in a case where 256transmission stations (including the master station) enter into thenetwork, the master station needs to perform 256 scans using SYN frames.In contrast, according to the present embodiment, once the masterstation transmits an SYN frame, each node returns an REQ frame accordingto its own transmission priority. This does not need to perform 256scans to reduce a transmission time. The address list setting circuitportion 100 will be described in detail hereinafter with reference tothe drawings.

The live list setting circuit portion 90 is a register (live list LL)that manages each logical address of transmission station set in theaddress list setting circuit portion 100. More specifically, the livelist setting circuit portion 90 manages the transmission priorities setin the address list setting circuit portion 100 by one-to-onerelationship between a logical address and a physical address of eachtransmission station (see FIG. 3). The logical address determiningcircuit portion 80 and the live list setting circuit portion 90 will bedescribed in detail later with reference to FIG. 4.

The logical address determining circuit portion 80 determines a logicaladdress which will be associated with a physical address M oftransmission station (node) carrying out a connection request, accordingto (i) information as to whether the communication port A or thecommunication port B receives a connection request frame (REQ frame) and(ii) a logical address V of transmission station that relays the REQframe and is adjacent to the transmission station (node), whoseinformation is included in the REQ frame, carrying out the connectionrequest. The logical address determining circuit portion 80 then setsthe physical address M in a transmission priority setting circuit 101corresponding to the determined logical address. The logical addressdetermining circuit portion 80 determines a logical address withreference to a condition FG shown in FIGS. 5, 6A and 6B. The conditionFG of FIG. 6A will be described in the second exemplary embodiment.

Frame format will be described later. Abbreviations stand for thefollowings.

Pre: a preamble

FCS: a frame check code

LL: a live list, “0” to “255”, 256 bits (valid/invalid 256 bits)

AL: an address list, “0” to “255”, 8 bits*256 (physical address)

M: a physical address of node/hub carrying out a connection request (“1”to “254”)

T: a type of node/hub carrying out a connection request (transmissionstation node/transmission station hub/branching station node)

V: a logical address of transmission station relaying an REQ frame (“1”to “255”)

N: a logical address of node/hub transmitting a CMP frame or an LPDframe (“1” to “254”)

JA: a star terminal logical address (“1” to “254”) of hub in case wherea transmission station hub relays an REQ frame from a branching stationnode carrying out a connection request;

a logical address (“1” to “254”) of transmission station hub relaying anREQ frame in case where a transmission station hub relays an REQ framefrom a transmission station node or a transmission station hub carryingout a connection request;

a fixed value (“255”) in a case where a transmission station node relaysan REQ frame from a branching station node carrying out a connectionrequest; and

a fixed value (“0”) in a case where a transmission station node relaysan REQ frame from a transmission station node or a transmission stationhub carrying out a connection request.

The condition FG is the followings.

(1) determining whether a master station is a transmission station node,a transmission station hub or a branching station node;

(2) determining whether a master station receives an REQ frame through acommunication port A, a communication port B or a star port (in a starconnection where branching station nodes are connected to a transmissionstation hub) thereof;

(3) determining whether a node transmitting an REQ frame is atransmission station node, a transmission station hub or a branchingstation node;

(4) determining whether an REQ frame is not relayed by any node (V=0)and is received by a master station or is relayed by any node (V≠0) andreceived by a master station (V: logical address of adjacent noderelaying it);

(5) determining whether a node (REQ relaying node) relaying an REQ frameis a transmission station node, a transmission station hub or nothing(nothing: a master station is adjacent to a node carrying out aconnection request and receives an REQ frame which is not relayed).

As shown in FIG. 5, a logical address is determined according to thedetermination result of condition FG. More specifically, in a case wherea transmission station or the like newly enters into the network (loop),in order to set logical addresses sequentially in order of entering intothe loop, the logical address determining circuit portion 80respectively shifts one or more physical addresses of transmissionstations, which have already entered into the loop and have beenregistered in one or more transmission priority setting circuits 101corresponding to one or more valid logical addresses equal to or morethan a logical address determined according to the determination resultof condition FG, to one ore more transmission priority setting circuits101 corresponding to new one or more logical addresses each of which hasa value generated by adding one to a value of each valid logical addressequal to or more than the determined logical address (“+1” shift). Thelogical address determining circuit portion 80 then registers a physicaladdress of the transmission station or the like newly entering into theloop in a transmission priority setting circuit 101 corresponding to thedetermined logical address.

In contrast, in a case where a transmission station withdraws from theloop, the logical address determining circuit portion 80 respectivelyshifts one ore more physical addresses of transmission stations, whichhave already entered into the loop and have been registered in one ormore transmission priority setting circuits 101 corresponding to one oremore valid logical addresses more than a logical address of thewithdrawing transmission station, to one ore more transmission prioritysetting circuits 101 corresponding to new one or more logical addresseseach of which has a value generated by subtracting one from a value ofeach valid logical address more than the logical address of thewithdrawing transmission station (“−1” shift). These determinations oflogical addresses will be described in “Description of operation ofentire system” in detail. These determinations of logical addresses arerealized using a hardware circuit and the determined logical addressesare set in the address list setting circuit portion 100.

FIG. 4 is a schematic structure diagram of the logical addressdetermining circuit portion 80 and the address list setting circuitportion 100. First, the address list setting circuit portion 100 will bedescribed.

As shown in FIG. 4, for example, the address list setting circuitportion 100 includes 256 transmission priority setting circuits (D-FFs)101 for setting a token order. These transmission priority settingcircuits 101 have respectively node addresses (logical addresses) froman end in series. The logical addresses represent a token order to bedetermined on the loop. More specifically, in a case where the maximumnumber of nodes is 256, the address list setting circuit portion 100includes 256 transmission priority setting circuits 101 each of whichhas an 8-bit D-FF (D-type flip-flop). Logical addresses “0”, “1”, “2”,“3”, “4” . . . “255” are sequentially assigned to the transmissionpriority setting circuits 101 from the end thereof. In the presentembodiment, a logical address “0” is assigned to a master station.

At a former stage of each transmission priority setting circuit 101,there are an order shift instructing circuit 105 and a physical addresshold instructing circuit 106. The order shift instructing circuit 105includes ANDs 102 a, 102 b and 102 c, an OR 103 and the like and shiftsa transmission priority. The physical address hold instructing circuit106 includes ANDs 106 a, 106 b and 106 c, an OR 107 and the like andholds a set physical address. The order shift instructing circuit 105 isconnected to the 8-bit D-FF via the physical address hold instructingcircuit 106.

When a synchronous node is established, an “address insert” becomesvalid in the logical address determining circuit portion 80, thereby theAND 102 c of the order shift instructing circuit 105 and the AND 106 bof the physical address hold instructing circuit 106 connected to thetransmission priority setting circuit 101 to which the logical address“0” is assigned become valid. Thereby, a physical address of thesynchronous node is held in the transmission priority setting circuit101 to which the logical address “0” is assigned.

In contrast, when a synchronous node withdraws, a “logical address −1shift” becomes valid in the logical address determining circuit portion80, thereby the AND 102 a of the order shift instructing circuit 105 andthe AND 106 b of the physical address hold instructing circuit 106connected to the transmission priority setting circuit 101 to which thelogical address “0” is assigned become valid. Thereby, a physicaladdress having been held in the transmission priority setting circuit101 to which the logical address “1” is assigned is held in thetransmission priority setting circuit 101 to which the logical address“0” is assigned.

When the logical address “1” is specified by an REQ frame in the logicaladdress determining circuit portion 80, an “address insert” becomesvalid in the logical address determining circuit portion 80, thereby theAND 102 c of the order shift instructing circuit 105 and the AND 106 bof the physical address hold instructing circuit 106 connected to thetransmission priority setting circuit 101 to which the logical address“1” is assigned become valid. Thereby, a physical address of a node,which carries out a connect request using the REQ frame, is held in thetransmission priority setting circuit 101 to which the logical address“1” is assigned.

In contrast, when a node to which the logical address “0” or “1” isassigned withdraws, a “logical address −1 shift” becomes valid in thelogical address determining circuit portion 80, thereby the AND 102 a ofthe order shift instructing circuit 105 and the AND 106 b of thephysical address hold instructing circuit 106 connected to thetransmission priority setting circuit 101 to which the logical address“1” is assigned become valid. Thereby, a physical address having beenheld in the transmission priority setting circuit 101 to which thelogical address “2” is assigned is held in the transmission prioritysetting circuit 101 to which the logical address “1” is assigned.

When the logical address “2” is specified by an REQ frame in the logicaladdress determining circuit portion 80, an “address insert” becomesvalid in the logical address determining circuit portion 80, thereby theAND 102 c of the order shift instructing circuit 105 and the AND 106 bof the physical address hold instructing circuit 106 connected to thetransmission priority setting circuit 101 to which the logical address“2” is assigned become valid. Thereby, a physical address of a node,which carries out a connect request using the REQ frame, is held in thetransmission priority setting circuit 101 to which the logical address“2” is assigned.

Further, when the logical address “1” is specified by the REQ frame inthe logical address determining circuit portion 80, a “logical address+1 shift” becomes valid in the logical address determining circuitportion 80, thereby the AND 102 b of the order shift instructing circuit105 and the AND 106 b of the physical address hold instructing circuit106 connected to the transmission priority setting circuit 101 to whichthe logical address “2” is assigned become valid. Thereby, a physicaladdress having been held in the transmission priority setting circuit101 to which the logical address “1” is assigned is held in thetransmission priority setting circuit 101 to which the logical address“2” is assigned.

When a node to which the logical address “0”, “1” or “2” is assignedwithdraws, a “logical address −1 shift” becomes valid in the logicaladdress determining circuit portion 80, thereby the AND 102 a of theorder shift instructing circuit 105 and the AND 106 b of the physicaladdress hold instructing circuit 106 connected to the transmissionpriority setting circuit 101 to which the logical address “2” isassigned become valid. Thereby, a physical address having been held inthe transmission priority setting circuit 101 to which the logicaladdress “3” is assigned is held in the transmission priority settingcircuit 101 to which the logical address “2” is assigned.

When the logical address “254” is specified by an REQ frame in thelogical address determining circuit portion 80, an “address insert”becomes valid in the logical address determining circuit portion 80,thereby the AND 102 c of the order shift instructing circuit 105 and theAND 106 b of the physical address hold instructing circuit 106 connectedto the transmission priority setting circuit 101 to which the logicaladdress “254” is assigned become valid. Thereby, a physical address of anode, which carries out a connect request using the REQ frame, is heldin the transmission priority setting circuit 101 to which the logicaladdress “254” is assigned.

When the logical addresses “1” to “253” are specified by REQ frames inthe logical address determining circuit portion 80, a “logical address+1 shift” becomes valid in the logical address determining circuitportion 80, thereby the AND 102 b of the order shift instructing circuit105 and the AND 106 b of the physical address hold instructing circuit106 connected to the transmission priority setting circuit 101 to whichthe logical address “254” is assigned become valid. Thereby, a physicaladdress having been held in the transmission priority setting circuit101 to which the logical address “253” is assigned is held in thetransmission priority setting circuit 101 to which the logical address“254” is assigned.

When a node to which the logical address “0”, “1”, “2” . . . or “254” isassigned withdraws, a “logical address −1 shift” becomes valid in thelogical address determining circuit portion 80, thereby the AND 102 a ofthe order shift instructing circuit 105 and the AND 106 b of thephysical address hold instructing circuit 106 connected to thetransmission priority setting circuit 101 to which the logical address“254” is assigned become valid. Thereby, a physical address having beenheld in the transmission priority setting circuit 101 to which thelogical address “255” is assigned is held in the transmission prioritysetting circuit 101 to which the logical address “254” is assigned.

When the logical address “255” is specified by an REQ frame in thelogical address determining circuit portion 80, an “address insert”becomes valid in the logical address determining circuit portion 80,thereby the AND 102 c of the order shift instructing circuit 105 and theAND 106 b of the physical address hold instructing circuit 106 connectedto the transmission priority setting circuit 101 to which the logicaladdress “255” is assigned become valid. Thereby, a physical address of anode, which carries out a connect request using the REQ frame, is heldin the transmission priority setting circuit 101 to which the logicaladdress “255” is assigned.

When the logical addresses “1” to “254” are specified by REQ frames inthe logical address determining circuit portion 80, a “logical address+1 shift” becomes valid in the logical address determining circuitportion 80, thereby the AND 102 b of the order shift instructing circuit105 and the AND 106 b of the physical address hold instructing circuit106 connected to the transmission priority setting circuit 101 to whichthe logical address “255” is assigned become valid. Thereby, a physicaladdress having been held in the transmission priority setting circuit101 to which the logical address “254” is assigned is held in thetransmission priority setting circuit 101 to which the logical address“255” is assigned.

When a node to which the logical address “0”, “1”, “2” . . . or “255” isassigned withdraws, a “logical address −1 shift” becomes valid in thelogical address determining circuit portion 80, thereby the AND 102 a ofthe order shift instructing circuit 105 and the AND 106 b of thephysical address hold instructing circuit 106 connected to thetransmission priority setting circuit 101 to which the logical address“255” is assigned become valid. Thereby, a value “0” is held in thetransmission priority setting circuit 101 to which the logical address“255” is assigned.

Since proceedings of an “address insert”, a “logical address −1 shift”and a “logical address +1 shift” for each of the logical addresses “3”to “253” are similar to those for the logical address “2” or “254”, thedescription is omitted.

When the logical address determining circuit portion 80 receives CMPframes and an REQ frame after an SYN frame appears, it performs theabove-described determinations to obtain a logical address to beassociated with a physical address of transmission station entering intoor withdrawing from the loop, and obtain a control value indicative of ashift direction (+1 shift or −1 shift) of physical addresses, which havebeen set in transmission priority setting circuits 101, to sequentiallyset the physical addresses in transmission priority setting circuits 101based on the obtained logical address and the obtained control value.

Next, the live list setting circuit portion 90 will be described withreference to FIG. 7. As shown in FIG. 7, the live list setting circuitportion 90 includes 256 D-FFs (D-type flip-flops) 901. Node addresses(logical addresses) “0” to “255” are sequentially assigned to the D-FFs901 in order of the arrangement of the transmission priority settingcircuits 101 in the address list setting circuit portion 100. Each D-FF901 holds information as to whether or not a logical address assigned toa corresponding transmission priority setting circuit 101 is valid.Every time when a transmission station enters into the loop, a valid bitis sequentially set in D-FFs 901.

The live list setting circuit portion 90 further includes write enablecircuits 910. Each write enable circuit 910 includes a correspondingaddress determining circuit 911, an AND 912, ORs 913 and 914, and asynchronous node determining circuit 915. The corresponding addressdetermining circuit 911 receives a logical address from the logicaladdress determining circuit portion 80 and determines whether or not thelogical address matches a logical address of corresponding D-FF 901previously set. The AND 912 carries out an AND operation for an outputsignal from the corresponding address determining circuit 911 and aphysical address of transmission station included in an REQ frame. Thesynchronous node determining circuit 915 receives a CMP frame from eachtransmission station and determines whether or not the CMP frame isnormally transmitted. The OR 914 carries out an OR operation for anoutput signal from the synchronous node determining circuit 915 and theoutput signal from the corresponding address determining circuit 911.The OR 913 carries out an OR operation for outputs from the AND 912 andthe OR 914 and outputs an output signal to the corresponding D-FF 901.

Namely, for each write enable circuit 910, if a valid value is held in acorresponding 8 bit D-FF 101 in the address list setting circuit portion100, a live list has a valid value “1”. If a valid value is not held ina corresponding 8 bit D-FF 101 in the address list setting circuitportion 100, a live list has an invalid value “0”.

The transmitting and receiving permission switch portion 10 is a controlcircuit for switching transmission and reception in a communication portbased on an instruction, signal from the MAC/DLC 50. The first receivingcontrol circuit portion 40 determines that a transmission frame is inputfrom either the communication port A or B. If there are transmissionframes input from the communication ports A and B, the first receivingcontrol circuit portion 40 switches one communication port from which atransmission frame is first input in preference to the other, until thereception is completed. An output from the first receiving controlcircuit portion 40 is input and reception-processed in the MAC/DLC 50.Although a terminal station can receive a transmission frame from eithera communication portion A or B due to the ring topology, the terminalstation normally turns off a reception permission switch at a side ofcommunication port in a blocking state and turns on a receptionpermission switch at a side of communication port in a non-blockingstate.

The transmitting and receiving control circuit portion (MAC/DLC) 50controls transmission and reception of a transmission frame based onEthernet (registered trademark) proceedings. The frame detectiondetermining circuit portion 60 is a circuit for detecting a frame suchas an SYN frame or a CMP frame. The frame data generating circuitportion 70 generates various frames according to addresses from the livelist setting circuit portion 90 and the address list setting circuitportion 100 and control data of the computer portion 110, and transmitsthem to the transmitting and receiving control circuit portion 50. Thecomputer portion 110 is a microprocessor that reads a necessary settingvalue and writes necessary data in a RAM according to programproceedings stored in a program memory (PROM and working RAM memory orPROM using RAM), and then temporarily holds or reads the necessary datato process it based on sequence proceedings or Ethernet (registeredtrademark) transmission proceedings in a transmission station. Forexample, the computer portion 110 transmits a physical address (uniquenumber of transmission station), which is set in the physical addresssetting portion 120, to the frame data generating portion 70, thelogical address determining circuit portion 80 or the like.

Each of nodes other than a master station has the same structure as themaster station. When the master station withdraws from the loop, a node(station) having the second highest transmission priority determines atransmission priority (logical address) for a node and associates alogical address with a physical address of the node. When the masterstation does not withdraw from the loop, each of nodes other than themaster station causes only a transmission priority setting circuit 101,which has a logical address of its own node, to be active in the addresslist setting circuit 100. Thereafter, a transmission priority isdetermined or a node to be set as a master station is determinedaccording to a state of live list LL.

(Description of Operation of Entire System)

An operation of the double-ring network system will be described below.For connection of transmission stations, it is desirable to constructthe B-system after the A-system is constructed or construct the A-systemafter the B-system is constructed. FIGS. 8 and 9 illustrate sequences ofan SYN frame (solid line) and a CMP frame (dotted line) in a case wherefive transmission stations enter into the loop. Each node generates aCMP frame or the like when an SYN frame is transmitted.

An outline at a time when a transmission station enters into the loopwill be described. In a first period during which an REQ frame istransmitted, a node (physical address M) which carries out a connectionrequest transmits an REQ frame during an LPD time. In a second periodduring which an REQ frame is transmitted, an adjacent node (N-th node)which receives the REQ frame from the node carrying out a connectionrequest relays the REQ frame to a synchronous node. In this way, atransmission frame is transmitted from a transmission station. FIGS. 11to 16 illustrate frame forms in a zero period to a fifth period as oneexample. Data, which is included in the REQ frame to be transmitted andrelayed, includes the physical address M of the node carrying out aconnection request. In a third period during which an REQ frame istransmitted, the synchronous node updates an address list AL.

An outline at a time when a transmission station withdraws from the loopwill be described. When the logical address determining circuit portion80 of a master station searches an address list AL (address list settingcircuit portion 100) in order of logical address and does not receive anormal CMP frame from a node, it deletes a physical address associatedwith a logical address corresponding to the node. Then, the logicaladdress determining circuit portion 80 respectively shifts physicaladdresses of other nodes, which have valid logical addresses more thanthe logical address corresponding to the node, to new logical addresseseach of which has a value generated by subtracting one from a value ofvalid logical address more than the logical address corresponding to thenode.

Frames generated by the frame data generating circuit portion 70 and thecomputer portion 110 will be described.

FIG. 10 is an explanatory diagram that illustrates an SYN frame.

A synchronous node generates either an SYN frame (Pre, . . . LL, FCS)shown in FIG. 10( a) or an SYNLST frame (Pre, . . . LL, AL, FCS) shownin FIG. 10( b) and transmits it. The SYNLST frame is constructed byadding an address list AL to the SYN frame. A scan synchronizesdepending on transmission of either the SYN frame or the SYNLST frame.

An REQ frame will be described. A physical address of a node carryingout a connection request is added in an address list AL using the REQframe (see FIG. 21). An REQ frame which will be described in the firstexemplary embodiment is shown in FIG. 21( a). An REQ frame which will bedescribed in the second exemplary embodiment is shown in FIG. 21( b). Inview of a case where a branching station is connected to a transmissionstation hub in a star connection structure, the REQ frame shown in FIG.21( b) is constructed by adding to the REQ frame shown in FIG. 21( a) aterminal logical address JA which indicates that the transmissionstation hub having a star connection structure has entered into a loop.The transmission station hub identifies a physical address of abranching station with reference to a LPD frame, searches (detects) anaddress list AL at a time of receiving SYNLST, and obtains a terminallogical address of the branching station following a logical address ofthe transmission station hub.

When a transmission station node or transmission station hub adjacent toa transmission station node, transmission station hub or branchingstation which transmits an REQ frame relays the REQ frame, the adjacenttransmission station node or transmission station hub adds to the REQframe a logical address associated with its own physical address in themaster station. Further, when a transmission station hub having a starconnection structure adjacent to a transmission station node ortransmission station hub which transmits an REQ frame relays the REQframe, the adjacent transmission station hub adds to the REQ frame aterminal logical address of branching station following a logicaladdress associated with its own physical address in the master station.

In the present embodiment, a synchronous node uses information of REQframe and determines which communication port A or B receives the REQframe (see FIG. 1). An REQ frame from a node adjacent to a synchronousnode is received during an LPD time. An REQ frame which an adjacent noderelays is received in slot time. FIGS. 17 to 19 are explanatory diagramseach of which illustrates an address list generated when a transmissionstation enters into a loop.

An operation at a time when a transmission station node “i” (1≦i≦5)enters into a loop will be described below in detail. Since operationsof ANDs, ORs and D-FFs in the live list setting circuit portion 90 andthe address list setting circuit portion 100, which will be describedbelow, are the same as those described above, the description ofoperations of them is omitted. It is noted that the master station maymange the following association between a physical address and a logicaladdress on software, using the live list LL and the address list ALshown in FIG. 3.

(Operation at Time when Transmission Station Enters into Loop)

FIG. 17 is an explanatory diagram that illustrates an address listgenerated when a transmission station enters into a loop. FIG. 17( a)shows an initial state of address list AL. In the address list AL, alltransmission priority setting circuits (8 bits D-FFs) 101 in the addresslist setting circuit portion 100 are tabulated in order of logicaladdresses. Numerical numbers “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7” . .. “254” and “255” are indicative of unique numbers (logical addresses)of the transmission priority setting circuit 101.

(Case 0: 6.0)

As shown in FIG. 17( b), when a transmission station node 1 enters intoa loop, the transmission station node 1 becomes a synchronous node andgenerates an SYN frame and a CMP frame (see FIG. 11, zero period). Asshown in FIG. 17( c), the logical address determining circuit portion 80transmits an address modification EN and a logical address determiningsignal and sets a physical address (1) of the transmission station node1 in a transmission priority setting circuit 101 to which a logicaladdress “0” is assigned. Thus, the logical address determining circuitportion 80 registers the physical address (1) in a transmission prioritysetting circuit 101 including an 8-bit D-FF to which the logical address“0” is assigned (the address modification is set to “change”, an addressinsertion, the address modification is set to “hold” after the physicaladdress (1) is output). At this time, a D-FF 901 having a logicaladdress “0” in the live list LL (live list setting circuit portion 90)becomes valid. In the case where the master station manages theassociation between a physical address and a logical address onsoftware, as shown in FIG. 17( d), the live list LL and the address listAL are set. It is noted that logical addresses are omitted in the secondor more rows in FIG. 17( d).

(Node-Communication Port A—Case 1: 6.1)

As shown in FIG. 17( e), a transmission station node 2 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. When the transmission station node 2 enters into theloop, the computer portion 110 of the transmission station node 1instructs the frame data generating circuit portion 70 to generate anSYN frame. The transmitting and receiving control circuit portion 50transmits the SYN frame to the communication ports A and B via thetransmitting and receiving permission switch 10. The computer portion110 of the transmission station node 2 instructs the frame datagenerating circuit portion 70 to generate an REQ frame. The transmittingand receiving control circuit portion 50 transmits the REQ frame to thecommunication port B via the transmitting and receiving permissionswitch 10 to transmit the REQ frame to the loop. At this time, thephysical address setting portion 120 sets a physical address in thecomputer portion 110. In the transmission station node (master station)1, the REQ frame is relayed through the transmitting and receivingpermission switch 10, the first receiving control circuit portion 40 andthe transmitting and receiving control circuit portion 50, and detectedin the frame detection determining circuit portion 60.

When the REQ frame is detected, the logical address determining circuitportion 80 determines where a physical address (2) of the transmissionstation node 2 newly entering into the loop will be inserted in theaddress list AL. In detail, the logical address determining circuitportion 80 determines the above-described condition FG ((1) to (5)). Ina case where the determination result of condition FG is a case 1 (6.1:a transmission node is transmission station node, an REQ frame isreceived in communication port A, and there is not an adjacent relaynode) in FIG. 5, the logical address determining circuit portion 80registers the physical address (2) in a transmission priority settingcircuit 101 to which the logical address “1” is assigned (the addressmodification is set to “change”, an address insertion, the addressmodification is set to “hold” after the physical address (2) is output).At this time, a D-ff 901 having a logical address “1” in the live listLL (live list setting circuit portion 90) becomes valid (a value “1” isassigned). In the case where the master station manages the associationbetween a physical address and a logical address on software the addresslist AL has a state shown in FIG. 17( f).

(Node-Communication Port B—Case 6: 6.2)

As shown in FIG. 18( a), a transmission station node 5 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 6 (6.2: atransmission node is transmission station node, an REQ frame is receivedin communication port B, and there is not an adjacent relay node) inFIG. 5, the logical address determining circuit portion 80 registers thephysical address (5), which is included in the REQ frame from thetransmission station node 5, in a transmission priority setting circuit101 to which the logical address “2” being a current terminal logicaladdress is assigned (the address modification EN is set to “change”, anaddress insertion, the address modification EN is set to “hold” afterthe physical address (5) is output). Although the physical address (5)should be associated with a logical address smaller than the logicaladdress “0” by one address, there is not the logical address smallerthan the logical address “0” by one address. Due to this, the logicaladdress determining circuit portion 80 associates the physical address(5) with the current terminal logical address. At this time, a D-FF 901having a logical address “2” in the live list LL (live list settingcircuit portion 90) becomes valid (a value “1” is assigned). In the casewhere the master station manages the association between a physicaladdress and a logical address on software, the address list AL has astate shown in FIG. 18( b).

(Node-Communication Port A—Case 2: 6.3)

As shown in FIG. 18( c), a transmission station node 3 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 2 (6.3: atransmission node is transmission station node, an REQ frame is receivedin communication port A, and an adjacent relay node is transmissionstation node) in FIG. 5, the logical address determining circuit portion80 shifts the physical address (5) registered in the transmissionpriority setting circuit 101 to which the logical address “2” isassigned, to a transmission priority setting circuit 101 to which alogical address “3” is assigned (“+1” shift, FIG. 18( d)), and thenregisters a physical address (3), which is included in the REQ framefrom the transmission station node 3, in the transmission prioritysetting circuit 101 to which the logical address “2” is assigned. Atthis time, a D-FF 901 having a logical address “3” in the live list LL(live list setting circuit portion 90) becomes valid (a value “1” isassigned). In the case where the master station manages the associationbetween a physical address and a logical address on software, theaddress list AL has a state shown in FIG. 18( e) through the processshown in FIG. 18( d).

Namely, when the REQ frame (M=(3), V=“1”), which is transmitted from thetransmission station node 3 (physical address (3)) and relayed by thetransmission station node 2 whose physical address (2) is registered inthe transmission priority setting circuit 101 to which the logicaladdress “1” is assigned, is input through the communication portion A,the logical address determining circuit portion 80 obtains a logicaladdress “V+1=2” generated by adding one to the logical address “V=1”.The logical address determining circuit portion 80 determines that thephysical address (5) set in the transmission priority setting circuit101 corresponding to the logical address “2” is a physical address to beshifted. Then, the logical address determining circuit portion 80 shiftsthe physical address (5) to the transmission priority setting circuit101 corresponding to the logical address “3” generated by adding one tothe logical address “2” and registers the physical address (3) in thetransmission priority setting circuit 101 corresponding to the logicaladdress “2” (the address modification EN is set to “change”, an addressinsertion, the address modification EN is set to “hold” after thephysical address (3) is output, see FIG. 18( e)). In FIG. 18( c),although a line is drawn such that a numerical number “2” surrounded bya dotted line moves, this does not indicate that the logical address “2”moves. This indicates that the logical address “2” is associated with aphysical address of a transmission station newly entering into the loop.FIGS. 18( f), 22(c), 22(e), 22(g), 23(a), 23(c), 23(e), 24(a), 24(c),24(e) and 26(a) have the same illustrations as FIG. 18( c).

(Node-Communication Port B—Case 7: 6.4)

As shown in FIG. 18( f), a transmission station node 4 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop (between the transmission station nodes 3 and 5). Thelogical address determining circuit portion 80 determines theabove-described condition FG ((1) to (5)). Ina case where thedetermination result of condition FG is a case 7 (6.4: a transmissionnode is transmission station node, an REQ frame is received incommunication port B, and an adjacent relay node is transmission stationnode) in FIG. 5, the logical address determining circuit portion 80shifts the physical address (5) registered in the transmission prioritysetting circuit 101 to which the logical address “3” is assigned, to atransmission priority setting circuit 101 to which a logical address “4”is assigned (“+1” shift, FIG. 18( g)), and then registers a physicaladdress (4), which is included in the REQ frame from the transmissionstation node 4, in the transmission priority setting circuit 101 towhich the logical address “3” is assigned (see FIG. 18( h)).

Namely, when the REQ frame (M=(4), V=“3”), which is transmitted from thetransmission station node 4 (physical address (4)) and relayed by thetransmission station node 5 whose physical address (5) is registered inthe transmission priority setting circuit 101 to which the logicaladdress “3” is assigned, is input through the communication portion B,the logical address determining circuit portion 80 obtains a logicaladdress “V=3”. The logical address determining circuit portion 80determines that the physical address (5) set in the transmissionpriority setting circuit 101 corresponding to the logical address “3” isa physical address to be shifted. Then, the logical address determiningcircuit portion 80 shifts the physical address (5) to the transmissionpriority setting circuit 101 corresponding to the logical address “4”generated by adding one to the logical address “3” and registers thephysical address (4) in the transmission priority setting circuit 101corresponding to the logical address “3” (the address modification EN isset to “change”, an address insertion, the address modification EN isset to “hold” after the physical address (4) is output, see FIG. 18(h)). At this time, a D-FF 901 having a logical address “4” in the livelist LL (live list setting circuit portion 90) becomes valid (a value“1” is assigned). In the case where the master station manages theassociation between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 18( h) throughthe process shown in FIG. 18( g). Finally, the live list LL and theaddress list AL have final states shown in FIG. 19. It is noted thatlogical addresses are omitted in the second or more rows in FIG. 19.

In contrast, in a case where a transmission station node withdraws fromthe loop, the logical address determining circuit portion 80respectively shifts one ore more physical addresses of transmissionstations, which have already entered into the loop and have beenregistered in one or more transmission priority setting circuits 101corresponding to one ore more valid logical addresses more than alogical address of the withdrawing transmission station, to one ore moretransmission priority setting circuits 101 corresponding to new one ormore logical addresses each of which has a value generated bysubtracting one from a value of each valid logical address more than thelogical address of the withdrawing transmission station (“−1” shift).

Accordingly, every time when a transmission station enters into a loop,a master station determines transmission priorities of transmissionstations according to a connection order in which the transmissionstations are connected to the loop, and sets the transmission prioritiesto the transmission stations. The transmission stations can sequentiallyreturn a frame according to transmission priorities (logical addresses)when receiving an SYN frame. This reduces a transmission time.

Second Exemplary Embodiment

FIG. 20 is a schematic structure diagram in a control method of adouble-ring network according to the second exemplary embodiments. Asthe second exemplary embodiment, it will be described that atransmission station hub “i” enters into a loop and branching stationnodes “i” are connected (star-like connected) to the transmissionstation hub “i”. In FIG. 20, a transmission station hub 1 is connectedbetween the transmission station nodes 2 and 3, and a transmissionstation hub 2 is connected between the transmission station nodes 4 and5. Branching station nodes 1 and 2 are star-like connected to thetransmission station hub 1. Branching station nodes 3 and 4 arestar-like connected to the transmission station hub 2. A master station1 has the same structure as the master station 1 shown in FIG. 1.

An operation at a time when a transmission station hub enters into aloop will be described below in detail, with reference to FIG. 22. Whena transmission station hub “i” enters into a loop, an REQ frame shown inFIG. 21( b) from the transmission station hub “1” is constructed byadding JA (star terminal logical address of hub) to the REQ frame shownin FIG. 21( a). The REQ frame is generated in a frame data generatingcircuit portion 70 of the transmission station hub “i”. In the presentembodiment, a physical address (1) of the master station is registeredin a transmission priority setting circuit 101 to which a logicaladdress “0” is assigned. A D-FF 901 having a logical address “0” in thelive list LL (live list setting circuit portion 90) becomes valid (avalue “1” is assigned).

(Node-Communication Port B—Case 6: 7.1)

As shown in FIG. 22( a), a transmission station node 7 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 6 (7.1: atransmission node is transmission station node, an REQ frame is receivedin communication port B, and there is not an adjacent relay node) inFIGS. 5 and 6, the logical address determining circuit portion 80registers the physical address (7), which is included in the REQ framefrom the transmission station node 7, in a transmission priority settingcircuit 101 to which the logical address “1” being a current terminallogical address is assigned (the address modification EN is set to“change”, an address insertion, the address modification EN is set to“hold” after the physical address (7) is output). At this time, a D-FF901 having a logical address “1” in the live list LL (live list settingcircuit portion 90) becomes valid (a value “1” is assigned), and thelogical addresses “0” and “1” are valid in the live list LL. In the casewhere the master station manages the association between a physicaladdress and a logical address on software, the address list AL has astate shown in FIG. 22( b).

(Node-Communication Port A—Case 1: 7.2)

As shown in FIG. 22( c), a transmission station node 2 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 1 (7.2: atransmission node is transmission station node, an REQ frame is receivedin communication port A, and there is not an adjacent relay node) inFIGS. 5 and 6, the logical address determining circuit portion 80 shiftsthe physical address (7) registered in the transmission priority settingcircuit 101 to which the logical address “1” is assigned, to atransmission priority setting circuit 101 to which a logical address “2”is assigned (“+1” shift, FIG. 22( d)), and then registers a physicaladdress (2), which is included in the REQ frame from the transmissionstation node 2, in the transmission priority setting circuit 101 towhich the logical address “1” is assigned (see FIG. 22( d)).

Namely, when the REQ frame (M=(2), V=“1”), which is transmitted from thetransmission station node 2 (physical address (2)) and is not relayed byany transmission station node, is input through the communicationportion A, the logical address determining circuit portion 80 obtains alogical address “1”. The logical address determining circuit portion 80determines that the physical address (7) set in the transmissionpriority setting circuit 101 corresponding to the logical address “1” isa physical address to be shifted. Then, the logical address determiningcircuit portion 80 shifts the physical address (7) to the transmissionpriority setting circuit 101 corresponding to the logical address “2”generated by adding one to the logical address “1” and registers thephysical address (2) in the transmission priority setting circuit 101corresponding to the logical address “1” (the address modification EN isset to “change”, an address insertion, the address modification EN isset to “hold” after the physical address (2) is output, see FIG. 22(d)). At this time, a D-FF 901 having a logical address “2” in the livelist LL (live list setting circuit portion 90) becomes valid (a value“1” is assigned); and the logical addresses “0”, to “2” are valid in thelive list LL. In the case where the master station manages theassociation between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 22( d).

(Node-Communication Port A—Connection Request Transmission StationHub-Case 2: 7.3)

As shown in FIG. 22( e), a transmission station hub 3 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 2 (7.3: atransmission node is transmission station hub, an REQ frame is receivedin communication port A, and an adjacent relay node is transmissionstation node) in FIG. 6A, the logical address determining circuitportion 80 shifts the physical address (7) registered in thetransmission priority setting circuit 101 to which the logical address“2” is assigned, to a transmission priority setting circuit 101 to whicha logical address “3” is assigned (“+1” shift), and then registers aphysical address (3), which is included in the REQ frame from thetransmission station hub 3, in the transmission priority setting circuit101 to which the logical address “2” is assigned.

Namely, when the REQ frame (M=(3), V=“1”), which is transmitted from thetransmission station hub 3 (physical address (3)) and relayed by thetransmission station node 2 whose physical address (2) is registered inthe transmission priority setting circuit 101 to which the logicaladdress “1” is assigned, is input through the communication portion A,the logical address determining circuit portion 80 obtains a logicaladdress “V+1=2” generated by adding one to the logical address “V=1”.The logical address determining circuit portion 80 determines that thephysical address (7) set in the transmission priority setting circuit101 corresponding to the logical address “2” is a physical address to beshifted. Then, the logical address determining circuit portion 80 shiftsthe physical address (7) to the transmission priority setting circuit101 corresponding to the logical address “3” generated by adding one tothe logical address “2” and registers the physical address (3) in thetransmission priority setting circuit 101 corresponding to the logicaladdress “2” (the address modification EN is set to “change”, an addressinsertion, the address modification EN is set to “hold” after thephysical address (3) is output, see FIG. 22( f)). At this time, a D-FF901 having a logical address “3” in the live list LL (live list settingcircuit portion 90) becomes valid (a value “1” is assigned), and thelogical addresses “0” to “3” are valid in the live list LL. In the casewhere the master station manages the association between a physicaladdress and a logical address on software, the address list AL has astate shown in FIG. 22( f).

(Node-Communication Port B—Connection Request Transmission StationHub-Case 7: 7.4)

As shown in FIG. 22( g), a transmission station hub 6 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop between the transmission station hub 3 and thetransmission station node 7. The logical address determining circuitportion 80 determines the above-described condition FG ((1) to (5)). Ina case where the determination result of condition FG is a case 7 (7.4:a transmission node is transmission station hub, an REQ frame isreceived in communication port B, and an adjacent relay node istransmission station node) in FIG. 6A, the logical address determiningcircuit portion 80 shifts the physical address (7) registered in thetransmission priority setting circuit 101 to which the logical address“3” is assigned, to a transmission priority setting circuit 101 to whicha logical address “4” is assigned (“+1” shift), and then registers aphysical address (6), which is included in the REQ frame from thetransmission station hub 6, in the transmission priority setting circuit101 to which the logical address “3” is assigned.

Namely, when the REQ frame (M=(6), V=“3”), which is transmitted from thetransmission station hub 6 (physical address (6)) and relayed by thetransmission station node 7 whose physical address (7) is registered inthe transmission priority setting circuit 101 to which the logicaladdress “3” is assigned, is input through the communication portion B,the logical address determining circuit portion 80 obtains a logicaladdress “V=3”. The logical address determining circuit portion 80determines that the physical address (7) set in the transmissionpriority setting circuit 101 corresponding to the logical address “3” isa physical address to be shifted. Then, the logical address determiningcircuit portion 80 shifts the physical address (7) to the transmissionpriority setting circuit 101 corresponding to the logical address “4”generated by adding one to the logical address “3” and registers thephysical address (6) in the transmission priority setting circuit 101corresponding to the logical address “3” (the address modification EN isset to “change”, an address insertion, the address modification EN isset to “hold” after the physical address (6) is output, see FIG. 22(h)). At this time, a D-FF 901 having a logical address “4” in the livelist LL (live list setting circuit portion 90) becomes valid (a value“1” is assigned), and the logical addresses “0” to “4” are valid in thelive list LL. In the case where the master station manages theassociation between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 22( h).

(Node-Communication Port A—Connection Request Branching StationNode-Case 5: 7.5)

As shown in FIG. 23( a), a branching station node 11 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). Ina case wherethe determination result of condition FG is a case 5 (7.5: atransmission node is branching station node, an REQ frame is received incommunication port A, and an adjacent relay node is transmission stationhub) in FIG. 6A, the logical address determining circuit portion 80respectively shifts the physical address (6) of transmission station hub6 and the physical address (7) of transmission station node 7, whichhave been registered in two transmission priority setting circuits 101corresponding to the logical addresses “3” and “4” equal to or more thanthe logical address “3” determined according to the determination resultof condition FG (within the valid logical addresses “0” to “4”), to twotransmission priority setting circuits 101 corresponding to two logicaladdresses “4” and “5” each of which has a value generated by adding oneto a value of each valid logical address equal to or more than thelogical address “3” (“+1” shift). The logical address determiningcircuit portion 80 then registers a physical address (11), which isincluded in the REQ frame from the branching station node 11, in thetransmission priority setting circuit 101 corresponding to the logicaladdress “3” (see FIG. 23( b)).

Namely, when the REQ frame (M=(11), V=“2”, T=branching station node),which is transmitted from the branching station node 11 (physicaladdress (11)) and relayed by the transmission station hub 3 whosephysical address (3) is registered in the transmission priority settingcircuit 101 to which the logical address “2” is assigned, is inputthrough the communication portion A, the logical address determiningcircuit portion 80 obtains a logical address “V+1=3” generated by addingone to the logical address “V=2”. The logical address determiningcircuit portion 80 determines that the physical addresses (6) and (7)set in the transmission priority setting circuits 101 corresponding tothe logical address “3” and “4” are physical addresses to be shifted.Then, the logical address determining circuit portion 80 respectivelyshifts the physical address (6) of transmission station hub 6 and thephysical address (7) of transmission station node 7, which have beenregistered in two transmission priority setting circuits 101corresponding to the logical addresses “3” and “4” equal to or more thanthe logical address “3” (within the valid logical addresses “0” to “4”),to two transmission priority setting circuits 101 corresponding to twological addresses “4” and “5” each of which has a value generated byadding one to a value of each valid logical address equal to or morethan the logical address “3”. The logical address determining circuitportion 80 then registers the physical address (11) in the transmissionpriority setting circuit 101 corresponding to the logical address “3”(the address modification EN is set to “change”, an address insertion,the address modification EN is set to “hold” after the physical address(11) is output, see FIG. 23( b)). At this time, a D-FF 901 having alogical address “5” in the live list LL (live list setting circuitportion 90) becomes valid (a value “1” is assigned), and the logicaladdresses “0” to “5” are valid in the live list LL. In the case wherethe master station manages the association between a physical addressand a logical address on software, the address list AL has a state shownin FIG. 23( b).

(Node-Communication Port A—there is Hub Relay-Case 3: 7.6)

As shown in FIG. 23( c), a transmission station node 4 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). Ina case wherethe determination result of condition FG is a case 3 (7.6: atransmission node is transmission station node, an REQ frame is receivedin communication port A, and an adjacent relay node is transmissionstation hub) in FIG. 6A, the logical address determining circuit portion80 respectively shifts the physical address (6) of transmission stationhub 6 and the physical address (7) of transmission station node 7, whichhave been registered in two transmission priority setting circuits 101corresponding to the logical addresses “4” and “5” equal to or more thanthe logical address “4” determined according to the determination resultof condition FG (within the valid logical addresses “0” to “5”), to twotransmission priority setting circuits 101 corresponding to the logicaladdresses “5” and “6” each of which has a value generated by adding oneto a value of each valid logical address equal to or more than thelogical address “4” (“+1” shift). The logical address determiningcircuit portion 80 then registers a physical address (4), which isincluded in the REQ frame from the transmission station node 4, in thetransmission priority setting circuit 101 corresponding to the logicaladdress “4” (see FIG. 23( d)).

Namely, when the REQ frame (M=(4), V=“2”, T=transmission station node,JA=“3”), which is transmitted from the transmission station node 4(physical address (4)) and relayed by the transmission station hub 3whose physical address (3) is registered in the transmission prioritysetting circuit 101 to which the logical address “2” is assigned, isinput through the communication portion A, the logical addressdetermining circuit portion 80 obtains a logical address “JA+1=4”generated by adding one to the logical address “JA=3”. The logicaladdress determining circuit portion 80 determines that the physicaladdresses (6) and (7) set in the transmission priority setting circuits101 corresponding to the logical addresses “4” and “5” are physicaladdresses to be shifted. Then, the logical address determining circuitportion 80 respectively shifts the physical address (6) of transmissionstation hub 6 and the physical address (7) of transmission station node7, which have been registered in two transmission priority settingcircuits 101 corresponding to the logical addresses “4” and “5” equal toor more than the logical address “4” (within the valid logical addresses“0” to “5”), to two transmission priority setting circuits 101corresponding to two logical addresses “5” and “6” each of which has avalue generated by adding one to a value of each valid logical addressequal to or more than the logical address “4”. The logical addressdetermining circuit portion 80 then registers the physical address (4)in the transmission priority setting circuit 101 corresponding to thelogical address “4” (the address modification EN is set to “change”, anaddress insertion, the address modification EN is set to “hold” afterthe physical address (4) is output, see FIG. 23( d)). At this time, aD-FF 901 having a logical address “6” in the live list LL (live listsetting circuit portion 90) becomes valid (a value “1” is assigned), andthe logical addresses “0” to “6” are valid in the live list LL. In thecase where the master station manages the association between a physicaladdress and a logical address on software, the address list AL has astate shown in FIG. 23( d).

(Node-Communication Port A—Connection Request Branching StationNode-Case 5: 7.7)

As shown in FIG. 23( e), a branching station node 12 transmits an REQframe to the communication port A of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 5 (7.7: atransmission node is branching station node, an REQ frame is received incommunication port A, and an adjacent relay node is transmission stationhub) in FIG. 6A, the logical address determining circuit portion 80respectively shifts the physical address (11) of branching station node11, the physical address (4) of transmission station node 4, thephysical address (6) of transmission station hub 6 and the physicaladdress (7) of transmission station node 7, which have been registeredin four transmission priority setting circuits 101 corresponding to thelogical addresses “3”, “4”, “5” and “6” equal to or more than thelogical address “3” determined according to the determination result ofcondition FG (within the valid logical addresses “0” to “6”), to fourtransmission priority setting circuits 101 corresponding to the logicaladdresses “4”, “5”, “6” and “7” each of which has a value generated byadding one to a value of each valid logical address equal to or morethan the logical address “3” (“+1” shift). The logical addressdetermining circuit portion 80 then registers a physical address (12),which is included in the REQ frame from the branching station node 12,in the transmission priority setting circuit 101 corresponding to thelogical address “3” (see FIG. 23( b)).

Namely, when the REQ frame (M=(12), V=“2”, T=branching station node),which is transmitted from the branching station node 12 (physicaladdress (12)) and relayed by the transmission station hub 3 whosephysical address (3) is registered in the transmission priority settingcircuit 101 to which the logical address “2” is assigned, is inputthrough the communication portion A, the logical address determiningcircuit portion 80 obtains a logical address “V+1=3” generated by addingone to the logical address “V=2”. The logical address determiningcircuit portion 80 determines that the physical addresses (11), (4), (6)and (7) set in the transmission priority setting circuits 101corresponding to the logical address “3”, “4”, “5” and “6” are physicaladdresses to be shifted. Then, the logical address determining circuitportion 80 respectively shifts the physical address (11) of branchingstation node 11, the physical address (4) of transmission station node4, the physical address (6) of transmission station hub 6 and thephysical address (7) of transmission station node 7, which have beenregistered in four transmission priority setting circuits 101corresponding to the logical addresses “3”, “4”, “5” and “6” equal to ormore than the logical address “3” (within the valid logical addresses“0” to “6”), to four transmission priority setting circuits 101corresponding to the logical addresses “4”, “5”, “6” and “7” each ofwhich has a value generated by adding one to a value of each validlogical address equal to or more than the logical address “3”. Thelogical address determining circuit portion 80 then registers thephysical address (12) in the transmission priority setting circuit 101corresponding to the logical address “3” (the address modification EN isset to “change”, an address insertion, the address modification EN isset to “hold” after the physical address (12) is output, see FIG. 23(f)). At this time, a D-FF 901 having a logical address “7” in the livelist LL (live list setting circuit portion 90) becomes valid (a value“1” is assigned), and the logical addresses “0” to “7” are valid in thelive list LL. In the case where the master station manages theassociation between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 23( f).

(Node-Communication Port B—There is Hub Relay-Case 7: 7.8)

As shown in FIG. 24( a), a transmission station node 5 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop between the transmission station node 4 and thetransmission station hub 6. The logical address determining circuitportion 80 determines the above-described condition FG ((1) to (5)). Ina case where the determination result of condition FG is a case 7 (7.8:a transmission node is transmission station node, an REQ frame isreceived in communication port B, and an adjacent relay node istransmission station hub) in FIG. 6A, the logical address determiningcircuit portion 80 respectively shifts the physical address (6) oftransmission station hub 6 and the physical address (7) of transmissionstation node 7, which have been registered in two transmission prioritysetting circuits 101 corresponding to the logical addresses “6” and “7”equal to or more than the logical address “6” determined according tothe determination result of condition FG (within the valid logicaladdresses “0” to “7”), to two transmission priority setting circuits 101corresponding to the logical addresses “7” and “8” each of which has avalue generated by adding one to a value of each valid logical addressequal to or more than the logical address “6” (“+1” shift). The logicaladdress determining circuit portion 80 then registers a physical address(5), which is included in the REQ frame from the transmission stationnode 5, in the transmission priority setting circuit 101 correspondingto the logical address “6” (see FIG. 24( b)).

Namely, when the REQ frame (M=(5), V=“6”), which is transmitted from thetransmission station node 5 (physical address (5)) and relayed by thetransmission station hub 6 whose physical address (6) is registered inthe transmission priority setting circuit 101 to which the logicaladdress “6” is assigned, is input through the communication portion B,the logical address determining circuit portion 80 obtains a logicaladdress “V=6”. The logical address determining circuit portion 80determines that the physical addresses (6) and (7) set in thetransmission priority setting circuits 101 corresponding to the logicaladdresses “6” and “7” are physical addresses to be shifted. Then, thelogical address determining circuit portion 80 respectively shifts thephysical address (6) of transmission station hub 6 and the physicaladdress (7) of transmission station node 7, which have been registeredin two transmission priority setting circuits 101 corresponding to thelogical addresses “6” and “7” equal to or more than the logical address“6” (within the valid logical addresses “0” to “7”), to two transmissionpriority setting circuits 101 corresponding to two logical addresses “7”and “8” each of which has a value generated by adding one to a value ofeach valid logical address equal to or more than the logical address“6”. The logical address determining circuit portion 80 then registersthe physical address (5) in the transmission priority setting circuit101 corresponding to the logical address “6” (the address modificationEN is set to “change”, an address insertion, the address modification ENis set to “hold” after the physical address (5) is output, see FIG. 24(b)). At this time, a D-FF 901 having a logical address “8” in the livelist LL (live list setting circuit portion 90) becomes valid (a value“1” is assigned), and the logical addresses “0” to “8” are valid in thelive list LL. In the case where the master station manages theassociation between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 24( b).

(Node-Communication Port B—Connection Request Branching StationNode-Case 9: 7.9)

As shown in FIG. 24( c), a branching station node 13 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). In a casewhere the determination result of condition FG is a case 9 (7.9: atransmission node is branching station node, an REQ frame is received incommunication port B, and an adjacent relay node is transmission stationhub) in FIG. 6A, the logical address determining circuit portion 80shifts the physical address (7) of transmission station node 7, whichhas been registered in the transmission priority setting circuit 101corresponding to the logical address “8” determined according to thedetermination result of condition FG, to a transmission priority settingcircuit 101 corresponding to a logical address “9” generated by addingone to the logical address “8” (“+1” shift). The logical addressdetermining circuit portion 80 then registers a physical address (13),which is included in the REQ frame from the branching station node 13,in the transmission priority setting circuit 101 corresponding to thelogical address “8” (see FIG. 24( d)).

Namely, when the REQ frame (M=(13), V=“7”, T=branching station node),which is transmitted from the branching station node 13 (physicaladdress (13)) and relayed by the transmission station hub 6 whosephysical address (6) is registered in the transmission priority settingcircuit 101 to which the logical address “7” is assigned, is inputthrough the communication portion B, the logical address determiningcircuit portion 80 obtains a logical address “V+1=8” generated by addingone to the logical address “V=7”. The logical address determiningcircuit portion 80 determines that the physical address (7) set in thetransmission priority setting circuits 101 corresponding to the logicaladdress “8” is a physical address to be shifted. Then, the logicaladdress determining circuit portion 80 shifts the physical address (7)of transmission station node 7, which has been registered in thetransmission priority setting circuit 101 corresponding to the logicaladdress “8”, to the transmission priority setting circuit 101corresponding to the logical address “9” generated by adding one to thelogical address “8”. The logical address determining circuit portion 80then registers the physical address (13) in the transmission prioritysetting circuit 101 corresponding to the logical address “8” (theaddress modification EN is set to “change”, an address insertion, theaddress modification EN is set to “hold” after the physical address (13)is output, see FIG. 24( d)). At this time, a D-FF 901 having a logicaladdress “9” in the live list LL (live list setting circuit portion 90)becomes valid (a value “1” is assigned), and the logical addresses “0”to “9” are valid in the live list LL. In the case where the masterstation manages the association between a physical address and a logicaladdress on software, the address list AL has a state shown in FIG. 24(d).

(Node-Communication Port B—Connection Request Branching StationNode-Case 9: 7.10)

As shown in FIG. 24( e), a branching station node 14 transmits an REQframe to the communication port B of the synchronous node and entersinto the loop. The logical address determining circuit portion 80determines the above-described condition FG ((1) to (5)). Ina case wherethe determination result of condition FG is a case 9 (7.10: atransmission node is branching station node, an REQ frame is received incommunication port B, and an adjacent relay node is transmission stationhub) in FIG. 6A, the logical address determining circuit portion 80respectively shifts the physical address (13) of branching station node13 and the physical address (7) of transmission station node 7 whichhave been registered in two transmission priority setting circuits 101corresponding to the logical addresses “8” and “9” equal to or more thanthe logical address “8” determined according to the determination resultof condition FG (within the valid logical addresses “0” to “9”), to twotransmission priority setting circuits 101 corresponding to the logicaladdresses “9” and “10” each of which has a value generated by adding oneto a value of each valid logical address equal to or more than thelogical address “8” (“+1” shift). The logical address determiningcircuit portion 80 then registers a physical address (14), which isincluded in the REQ frame from the branching station node 14, in thetransmission priority setting circuit 101 corresponding to the logicaladdress “8” (see FIG. 24( f)).

Namely, when the REQ frame (M=(14), V=“7”, T=branching station node),which is transmitted from the branching station node 14 (physicaladdress (14)) and relayed by the transmission station hub 6 whosephysical address (6) is registered in the transmission priority settingcircuit 101 to which the logical address “7” is assigned, is inputthrough the communication portion B, the logical address determiningcircuit portion 80 obtains a logical address “V+1=8” generated by addingone to the logical address “V=7”. The logical address determiningcircuit portion 80 determines that the physical addresses (13) and (7)set in the transmission priority setting circuits 101 corresponding tothe logical address “8” and “9” are physical addresses to be shifted.Then, the logical address determining circuit portion 80 respectivelyshifts the physical address (13) of branching station node 13 and thephysical address (7) of transmission station node 7, which have beenregistered in two transmission priority setting circuits 101corresponding to the logical addresses “8” and “9” equal to or more thanthe logical address “8” (within the valid logical addresses “0” to “9”),to two transmission priority setting circuits 101 corresponding to thelogical addresses “9” and “10” each of which has a value generated byadding one to a value of each valid logical address equal to or morethan the logical address “8”. The logical address determining circuitportion 80 then registers the physical address (14) in the transmissionpriority setting circuit 101 corresponding to the logical address “8”(the address modification EN is set to “change”, an address insertion,the address modification EN is set to “hold” after the physical address(14) is output, see FIG. 24( f)). At this time, a D-FF 901 having alogical address “10” in the live list LL (live list setting circuitportion 90) becomes valid (a value “1” is assigned), and the logicaladdresses “0” to “10” are valid in the live list LL. In the case wherethe master station manages the association between a physical addressand a logical address on software, the address list AL has a state shownin FIG. 24( f).

Finally, the live list LL and the address list AL have final statesshown in FIG. 25. FIG. 25( a) shows a final connection topology. FIG.25( b) shows the final state of live list LL. FIG. 25( c) shows thefinal state of address list AL.

(Example of Withdrawing from Loop)

Next, withdrawing from a loop will be described. With reference to FIG.25( a), a case (deactivated case) where the transmission station hub(physical address (6)) withdraws from the loop will be described (seeFIG. 26( a)). In this case, there is not a CMP frame from thetransmission station hub (physical address (6)). At this time, thelogical address “7” becomes empty in the address list.

When the transmission station hub (physical address (6)) withdraws fromthe loop, the physical address which is registered in the transmissionpriority setting circuit 101 to which the logical address “7” isassigned is cleared (there is not the transmission station hub (physicaladdress (6))). Then, the logical address determining circuit portion 80obtains logical addresses assigned to transmission priority settingcircuits 101 which will newly register the physical addresses havingbeen registered in the transmission priority setting circuits 101 towhich the valid logical addresses equal to or more than the logicaladdress “8” (=“7”+1) are assigned, by carrying out the “logical address−1 shift”.

In detail, the logical address determining circuit portion 80 obtainsthe logical addresses “7” (=“8“−”1”), “8” (=“9“−”1”) and “9” (=“10“−”1”)because the logical addresses “8”, “9” and “10” are valid, and thenshifts the physical address (14), which has been registered in thetransmission priority setting circuit 101 to which the logical address“8” is assigned, to the transmission priority setting circuit 101 towhich the logical address “7” is assigned; shifts the physical address(13), which has been registered in the transmission priority settingcircuit 101 to which the logical address “9” is assigned, to thetransmission priority setting circuit 101 to which the logical address“8” is assigned; and shifts the physical address (7), which has beenregistered in the transmission priority setting circuit 101 to which thelogical address “10” is assigned, to the transmission priority settingcircuit 101 to which the logical address “9” is assigned (see FIG. 26(b)). Namely, the logical address determining circuit portion 80subtracts one from each of values of valid logical addresses equal to ormore than “8”, and then sequentially shifts the physical addresses,which have been registered in the transmission priority setting circuits101 to which the valid logical addresses equal to or more than thelogical address “8” are assigned, to transmission priority settingcircuits 101 to which the logical addresses obtained by the subtractionare assigned. In the case where the master station manages theassociation between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 26( b).

Next, a case (deactivated case) where the branching station node(physical address (14)) withdraws from the loop will be described (seeFIG. 26( c)). In this case, there is not a CMP frame from the branchingstation node (physical address (14)). At this time, the logical address“7” becomes empty in the address list.

When the branching station node (physical address (14)) withdraws fromthe loop, the physical address which is registered in the transmissionpriority setting circuit 101 to which the logical address “7” isassigned is cleared (there is not the branching station node (physicaladdress (14))). Then, the logical address determining circuit portion 80obtains logical addresses assigned to transmission priority settingcircuits 101 which will newly register the physical addresses havingbeen registered in the transmission priority setting circuits 101 towhich the valid logical addresses equal to or more than the logicaladdress “8” (=“7”+1) are assigned, by carrying out the “logical address−1 shift”.

In detail, the logical address determining circuit portion 80 obtainsthe logical addresses “7” (=“8“−”1”) and “8” (=“9“−”1”) because thelogical addresses “8” and “9” are valid, and then shifts the physicaladdress (13), which has been registered in the transmission prioritysetting circuit 101 to which the logical address “8” is assigned, to thetransmission priority setting circuit 101 to which the logical address“7” is assigned; and shifts the physical address (7), which has beenregistered in the transmission priority setting circuit 101 to which thelogical address “9” is assigned, to the transmission priority settingcircuit 101 to which the logical address “8” is assigned (see FIG. 26(d)). Namely, the logical address determining circuit portion 80subtracts one from each of values of valid logical addresses equal to ormore than logical address “8”, and then sequentially shifts the physicaladdresses, which have been registered in the transmission prioritysetting circuits 101 to which the valid logical addresses equal to ormore than the logical address “8” are assigned, to transmission prioritysetting circuits 101 to which the logical addresses obtained by thesubtraction are assigned. In the case where the master station managesthe association between a physical address and a logical address onsoftware, the address list AL has a state shown in FIG. 26( d).

Next, a case (deactivated case) where the branching station node(physical address (13)) withdraws from the loop will be described (seeFIG. 26( e)). In this case, there is not a CMP frame from the branchingstation node (physical address (13)). At this time, the logical address“7” becomes empty in the address list.

When the branching station node (physical address (13)) withdraws fromthe loop, the physical address which is registered in the transmissionpriority setting circuit 101 to which the logical address “7” isassigned is cleared (there is not the branching station node (physicaladdress (13))). Then, the logical address determining circuit portion 80obtains a logical address assigned to a transmission priority settingcircuit 101 which will newly register the physical address having beenregistered in the transmission priority setting circuit 101 to which thelogical address “8” (=“7”+1) is assigned, by carrying out the “logicaladdress −1 shift”.

In detail, the logical address determining circuit portion 80 obtainsthe logical addresses “7” (=“8“−”1”) because the logical address “8” isvalid, and then shifts the physical address (7), which has beenregistered in the transmission priority setting circuit 101 to which thelogical address “8” is assigned, to the transmission priority settingcircuit 101 to which the logical address “7” is assigned (see FIG. 26(f)). Namely, the logical address determining circuit portion 80subtracts one from the logical address “8”, and then shifts the physicaladdress, which has been registered in the transmission priority settingcircuit 101 to which the logical address “8” is assigned, totransmission priority setting circuit 101 to which the logical addressobtained by the subtraction is assigned. In the case where the masterstation manages the association between a physical address and a logicaladdress on software, the address list AL has a state shown in FIG. 26(f).

Accordingly, even if a transmission station hub enters into a loop, atransmission priority of the transmission station hub is determinedaccording to a connection order. Ina case where a branching station nodeis connected (star-like connected) to a transmission station hub, atransmission priority of the branching station node is determined,following a transmission priority of the transmission station hub.Namely, in a state where the transmission priority setting circuits 101are sequentially arranged, a transmission priority of transmissionstations is determined according to the arrangement sequence oftransmission priority setting circuits 101 without depending on physicaladdresses M of the transmission stations, and then the determinedtransmission priority is set to each node. Thus, each transmissionstation can transmit a transmission frame based on its own transmissionpriority according to a reception of SYN frame, which reduces atransmission time.

For example, in a case where 256 transmission stations (including amaster station) enter into a loop, the master station needs to perform256 scans using SYN frames because the master station receives an REQframe from only a node eligible to transmit a frame in MAC control time.In contrast, in the present embodiments, when a master station transmitsan SYN frame, each node returns an REQ frame according to a connectionorder. This can reduce a transmission time (the master station does notneed to perform 256 scans).

Other Exemplary Embodiment

While certain embodiments have been described, there embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

According to a double-ring network system, a method for determining atransmission priority in a double-ring network, and a transmissionstation device of at least one embodiment described above, atransmission time is automatically reduced even if a transmissionstation is changed or added.

What is claimed is:
 1. A double-ring network system comprising one ormore transmission stations each of which is connected to a double-ringnetwork and includes two communication ports allowing two-waycommunication, wherein: any one of the one or more transmission stationsfunctions as a master station; a new transmission station, which entersinto the double-ring network, transmits a connection request frameincluding a physical address of the new transmission station, accordingto a reception of a synchronous frame from the master station; themaster station associates the transmitted physical address with alogical address for determining a transmission priority of eachtransmission station connected to the double-ring network, to determinea transmission priority of the new transmission station; and the masterstation comprises: a transmitting and receiving portion that controls atransmission and reception timing, transmits a generated frame from thetwo communication ports, and introduces therein a frame received via thedouble-ring network according to a transmission of a synchronous frame;a frame detection determining circuit portion that determines whether ornot the transmitting and receiving portion receives the connectionrequest frame; an address list setting circuit portion that includestransmission priority setting circuits to which logical addresses aresequentially assigned, and transmits a physical address of atransmission station set in each transmission priority setting circuitand a logical address of the each transmission priority setting circuitin which the physical address of the transmission station is set; alogical address determining circuit portion that determines, when theframe detection determining circuit portion receives the connectionrequest frame, a logical address whose a value corresponds to aconnection number of the new transmission station such that transmissionpriorities of transmission stations match a connection order on thedouble-ring network, based on a communication port via which theconnection request frame is received, and sets the physical addressincluded in the connection request frame in a transmission prioritysetting circuit to which the determined logical address is assigned; anda frame data generating circuit portion that generates a synchronousframe to which a physical address and a logical address from the addresslist setting circuit are added, and instructs the transmitting andreceiving portion to transmit the generated synchronous frame.
 2. Thedouble-ring network system according to claim 1, wherein: the masterstation further includes a live list setting circuit portion that hasholding circuits corresponding to the transmission priority settingcircuits; and every time when the connection request frame is receivedand a physical address is set in a transmission priority settingcircuit, the master station sequentially validates a holding circuitcorresponding to the transmission priority setting circuit.
 3. Thedouble-ring network system according to claim 2, wherein when atransmission station withdraws, a holding circuit corresponding to atransmission priority setting circuit in which a physical address is notset is invalidated.
 4. The double-ring network system according to claim1, wherein the logical address determining circuit portion obtainslogical addresses generated by adding one to each of logical addressesequal to or more than a logical address to be associated with a physicaladdress included in the connection request frame, and sequentiallyshifts physical addresses set in transmission priority setting circuitsto which the logical addresses more than or equal to the logical addressare assigned, to transmission priority setting circuits to which theobtained logical addresses are assigned.
 5. A method for determining atransmission priority of a transmission station connected to adouble-ring network system to which one or more transmission stationseach of which is connected to the double-ring network and includes twocommunication ports allowing two-way communication are connected,wherein any one of the one or more transmission stations functions as amaster station, the method comprising: generating, via the masterstation, an address list in which one or more logical addresses fordetermining one or more transmission priorities of the one or moretransmission stations connected to the double-ring network are arrangedin ascending order; transmitting, via the master station, to the one ormore transmission stations connected to the double-ring network asynchronous frame which includes therein the one or more logicaladdresses associated with one or more physical addresses of the one ormore transmission stations; transmitting, via a new transmission stationto be connected to the double-ring network, to the master station aconnection request frame which includes a physical address of the newtransmission station; setting, when each transmission station other thanthe master station receives the synchronous frame, a logical addressincluded in the synchronous frame as a transmission priority of the eachtransmission station and transmitting, via the each transmissionstation, a frame data to the master station according to its owntransmission priority; associating, via the master station, on theaddress list the physical address included in the connection requestframe transmitted from the new transmission station according to atransmission of the synchronous frame, with a logical address whose avalue corresponds to a connection number of the new transmission stationsuch that transmission priorities of transmission stations match aconnection order on the double-ring network, based on a communicationport via which the connection request frame is received; obtaining, viathe master station, when receiving the connection request frame in astate where physical addresses are assigned on the address list, logicaladdresses generated by adding one to each of logical addresses equal toor more than the logical address associated with the physical addressincluded in the connection request frame, and associating with theobtained logical addresses physical addresses associated with thelogical addresses equal to or more than the logical address; andtransmitting, via the master station, every time when a physical addressis assigned on the address list, to the double-ring network thesynchronous frame to which the physical address and a logical addressassociated with the physical address are added.
 6. The method accordingto claim 5, further comprising: adding, via at least one of the one ormore transmission stations, when receiving the connection request framefrom an adjacent transmission station, to the connection request frame alogical address which is associated with a physical address of the atleast one of the one or more transmission stations in the masterstation, and relaying the connection request frame to the masterstation.
 7. The method according to claim 5, wherein at least one of theone or more transmission stations is a hub station or a branchingstation connected to the hub station.
 8. A transmission station devicewhich is connected to a double-ring network and includes twocommunication ports allowing two-way communication, the transmissionstation device comprising: a transmitting and receiving portion thatcontrols a transmission and reception timing, transmits a generatedframe from the two communication ports, and introduces therein a framereceived via the double-ring network according to a transmission of asynchronous frame; a frame detection determining circuit portion thatdetermines whether or not the transmitting and receiving portionreceives a connection request frame from a new transmission station; anaddress list setting circuit portion that includes transmission prioritysetting circuits to which logical addresses indicative of transmissionpriorities on the double-ring network are sequentially assigned, andtransmits a physical address of a transmission station set in eachtransmission priority setting circuit and a logical address of the eachtransmission priority setting circuit in which the physical address ofthe transmission station is set; a logical address determining circuitportion that determines, when the frame detection determining circuitportion receives the connection request frame, a logical address whose avalue corresponds to a connection number of the new transmission stationsuch that transmission priorities of transmission stations match aconnection order on the double-ring network, based on a communicationport via which the connection request frame is received, and sets thephysical address included in the connection request frame in atransmission priority setting circuit to which the determined logicaladdress is assigned; and a frame data generating circuit portion thatgenerates a synchronous frame to which a physical address and a logicaladdress from the address list setting circuit are added, and instructsthe transmitting and receiving portion to transmit the generatedsynchronous frame.
 9. The transmission station device according to claim8, further comprising a live list setting circuit portion that hasholding circuits corresponding to the transmission priority settingcircuits; wherein every time when the connection request frame isreceived and a physical address is set in a transmission prioritysetting circuit, a holding circuit corresponding to the transmissionpriority setting circuit is sequentially validated.
 10. The transmissionstation device according to claim 9, wherein when a transmission stationwithdraws, a holding circuit corresponding to a transmission prioritysetting circuit in which a physical address is not set is invalidated.11. The transmission station device according to claim 8, wherein thelogical address determining circuit portion obtains logical addressesgenerated by adding one to each of logical addresses equal to or morethan a logical address to be associated with a physical address includedin the connection request frame, and sequentially shifts physicaladdresses set in transmission priority setting circuits to which thelogical addresses more than or equal to the logical address areassigned, to transmission priority setting circuits to which theobtained logical addresses are assigned.